1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of designing the semiconductor integrated circuit for a purpose of protecting a gate oxide film of a transistor.
2. Description of the Related Art
In recent years, miniaturization of constituent elements in a semiconductor integrated circuit has been largely advanced. Above all, film thinning has been remarkably progressed in a gate oxide film in an MOS (Metal Oxide Semiconductor) transistor. However, thinning of the gate oxide film leads to reduction of a withstanding voltage of the gate oxide film and may cause the time dependent dielectric breakdown (TDDB) when a voltage is applied. Therefore, caution for the time dependent dielectric breakdown (TDDB) should be needed with respect to a circuit where a power supply voltage is constantly applied to a gate. Examples of such a circuit are a decoupling capacitance cell, a correction cell and the like.
The decoupling capacitance cell is provided in order to control variations of the power supply voltage that have become distinguished based on a large scale and high speed of SOC (system on a chip). In the decoupling capacitance, an MOS transistor of P-channel type or N-channel type is provided, and then a drain and a source thereof are connected to a high-voltage power supply wiring or a low-voltage power supply wiring so that a voltage of a reverse polarity is applied to a gate thereof.
A correction cell is the cell used in the case where an operation defect and addition of a function are generated after cell alignment wiring is implemented in a logical block. When the correction cell is not being used, a gate thereof is fixed to the power supply voltage or ground voltage in order to avoid increase of malfunction and power consumption due to a gate floating.
FIG. 11 is a circuit diagram of a TDDB control cell A1′ provided with a decoupling capacitance that is an example of a conventional semiconductor integrated circuit. FIG. 12 is a layout plan view of the TDDB control cell A1′. The TDDB control cell A1 solves the foregoing problem (TDDB) through including the circuit recited in U.S. Pat. No. 4,868,903.
The TDDB control cell A1′ comprises a TDDB control circuit 1 and a decoupling capacitance circuit 2 connected to the TDDB control circuit 1. The TDDB control circuit 1 includes a first transistor QP1 of P-channel type and a second transistor QN2 of N-channel type wherein a gate of the first transistor QP1 is connected to a drain of the second transistor QN2, and a drain of the first transistor QP1 is connected to a gate of the second transistor QN2.
The decoupling capacitance circuit 2 includes a third transistor QP3 of the P-channel type and a fourth transistor QN4 of the N-channel type wherein a source and a drain of the third transistor QP3 are connected to the high-voltage power supply wiring (VDD), and a drain and a source of the fourth transistor QN4 are connected to the low-voltage power supply wiring. A gate of the third transistor QP3 is connected to the drain of the second transistor QN2 through a wiring 52, and a gate of the fourth transistor QN4 is connected to the drain of the first transistor QP1 through a wiring 51. The power supply voltage (VDD/VSS) is constantly applied to the gates of the third transistor QP3 and the fourth transistor QN4.
Through providing the TDDB control circuit 1, the TDDB deterioration, that has the potential of generating in the decoupling capacitance circuit 2 where the power supply voltage is constantly applied to the gate, can be prevented.
However, the conventional semiconductor integrated circuit provided with the TDDB control circuit in the decoupling capacitance circuit that requires the protection of a gate insulating film is in a complete form itself. In other words, the conventional semiconductor circuit is provided independently under irrelevant state from the cells such as the other decoupling capacitance cell, correction cell and the like provided in a chip wherein prevention of the TDDB deterioration is requested. As a result, it becomes necessary to add the TDDB control circuit individually in each of the cells where prevention of the TDDB deterioration is requested, which is an unfavorable factor for increase of a chip area.